Classification of operational amplifiers

High-speed broadband operational amplifiers (K154UD2) are used to convert rapidly changing signals. They are characterized by high slew rate, fast settling time, high unity gain frequency, and are inferior to general purpose operational amplifiers in other parameters. Unfortunately, recovery time after overload is not standardized for them. Their main parameters are: slew rate VUout max >> 30 V/µs; settling time tset ≤ 1 µs; unity gain frequency f1 ≥ 10 MHz.

Precision (high-level) operational amplifiers (K140UD24) are used to amplify small electrical signals accompanied by a high level of noise, and are characterized by a low bias voltage and its temperature drift, high gain and common mode signal suppression, high input impedance and low noise. As a rule, they have low performance. Their main parameters are: bias voltage Ucm ≤ 250 μV; temperature drift ΔUcm / ΔT ≤ 5 µV/°С; gain KU0 ≥ 150k

Operational amplifiers for general use (K140UD7) are used to build equipment nodes with a total reduced error of 1%. They are characterized by a relatively low cost and an average level of parameters (bias voltage Ucm – a few millivolts, temperature drift ΔUcm / ΔT – tens of microvolts / ° C, gain KU0 – tens of thousands, slew rate VUout max – from tenths to a few volts / microseconds).

Operational amplifiers with low input current – amplifiers with an input stage built on field-effect transistors. Input current Iin ≤ 100 pA.

Multi-channel op amps are similar in performance to general purpose or micropower amplifiers, with the addition of a crossover factor. They serve to improve the weight and size indicators and reduce the power consumption of the equipment. Western firms produce dual precision and high-speed amplifiers.

Powerful and high-voltage operational amplifiers – amplifiers with output stages built on powerful high-voltage elements. Output current Iout ≥ 100 mA; output voltage Uout ≥ 15 V.

48 Micropower operational amplifiers (K1423UD1) are necessary in cases where the power consumption is strictly limited (portable devices with self-powered devices, devices operating in standby mode). Current consumption Ipot max ≤ 1 mA.


Comparators are a special class of electronic circuits, the main function of which is to compare the input signal with the reference one. In them, the state of the output signal changes when the input signal exceeds the threshold value (Fig. 6.14). Comparators can be based on various elements, including operational amplifiers. In this case, the amplification of the input signal is significant only near the threshold, mainly the work of the op-amp occurs in the region of the output voltage limitation (negative or positive).

The figure shows the LM311 comparator:

Figure 6.14 How the comparator works.

The main characteristic of the comparator is the “input-output” dependence (the dependence of the output voltage on the input voltage), shown in fig. 6.15

Rice. 6.15. Dependence “input-output” for the comparator.

The circuit of the simplest zero level detector comparator (the threshold voltage is close enough to zero) is shown in Figure 6.16

Rice. 6.16. Scheme of inclusion of the comparator.

An electronic generator is an electronic device that generates electrical oscillations of a certain frequency and shape using the energy of a constant voltage (current) source. There are generators with self-excitation ( autogenerators ) and generators with external excitation . Any self-oscillator contains an oscillatory system and an amplifying element (based on a bipolar or field-effect transistor) connected by positive feedback. The main characteristics of the generator are the shape, frequency and power of oscillations. According to the form, electronic generators of harmonic (almost sinusoidal) oscillations and the so-called relaxation generators of various shapes are distinguished.

The comparator model in the Multisim environment is shown in fig. 6. 17, oscilloscope readings in fig. 6.18.

Rice. 6.17. Comparator in Multisim environment

Rice. 6.18. Oscilloscope readings at the input / output of the comparator

Voltage regulator

A voltage stabilizer is a converter of electrical energy that allows you to get an input voltage that is in the specified large fluctuations in the input voltage and load resistance. According to the type of output voltage, stabilizers are divided into DC and AC stabilizers. As a rule, the type of supply is the same as the output voltage, although exceptions are possible.

Consider a DC stabilizer – a linear stabilizer (Fig. 6.19). It is a voltage divider, the input of which is supplied with an input (unstable) voltage, and the output (stabilized) voltage is taken from the lower arm of the divider. Stabilization is carried out by changing the resistance of one of the divider arms: the resistance is constantly maintained so that the voltage at the output of the stabilizer is within the established limits. With a large ratio of input / output voltages, the linear stabilizer has a low efficiency, since most of the power P diss u003d (U in – U out ) * I t is dissipated in the form of heat on the control element. Therefore, the regulating element must be able to dissipate sufficient power, that is, it must be installed on a radiator of the required area. The advantage of a linear stabilizer is simplicity, lack of interference and a small number of parts used.

Rice. 6.19. Chip linear stabilizer KR1170EN8

Depending on the location of the element with variable resistance, linear stabilizers are divided into two types:

· In series: the regulating element is connected in series with the load.

· Parallel: the regulating element is connected in parallel with the load.

Depending on the stabilization method:

· Parametric: in such a stabilizer, the I–V characteristic of the device is used, which has a large steepness.

· Compensatory: has feedback. In it, the voltage at the output of the stabilizer is compared with the reference one, from the difference between them a control signal is formed for the regulating element.

On fig. 6.20 models are presented: a) a parallel parametric stabilizer on a zener diode; b) sequential compensation stabilizer at the OS.

Rice. 6. 20. a) Model of a parallel parametric stabilizer on a zener diode

Rice. 6. 20. b) Model of a series compensation stabilizer on the OS

The stabilizer can also be built using an integrated circuit (shown in the figure), for example, LM7812CT – a linear voltage regulator. The model is shown in fig. 6.21.

Rice. 6.21. Model of the stabilizer on an integrated circuit

Digital devices

Digital devices are devices designed to form, convert and transmit code words. At the same time, code words (codes or numbers) in electronic digital devices are presented as sequences of electrical impulses (signals with two voltage levels: high and low), and their transformations are carried out by arithmetic, logic, storage and auxiliary devices.

The elements and nodes of digital devices that serve as the basis for building microprocessors, microprocessor systems, computers, automated control systems for objects, technological processes and information flows are: decoders, adders, triggers, registers, counters and many others.

The basic elementary units of digital circuits, such as the elements “AND”, “OR”, “NOT”, are in the section Misc Digital, subsection TIL.

Let’s consider each of them separately:

Based on the basic elements, we will create a diagram of a digital device for making a decision on the condition. The block diagram of such a device is shown in fig. 6.22. The condition will be set by a logical expression:

Rice. 6.22. Block diagram of a digital device

The model obtained in Multisim is displayed in fig. 6. 23. The outputs will go high (5V) when the input configuration satisfies the specified condition.

Rice. 6.23. Device Model in Multisim

Now consider the scheme and mechanism of operation of a frequently used device – a multiplexer – a channel switch. The block diagram is shown in fig. 6.21. There are two basic elements in the diagram – a switch and a switch. The switch is made in the form of a key with signals x1 and x2, it determines which of the four channels is connected to the output at the moment. In key position 00 (address code x1 = 0, x2 = 0) y = a; in position 01 (x1 = 0, x2 = 1) y = b; in position 10 (x1 = 1, x2 = 0) y = c; in position 11 (x1 = 1, x2 = 1) y = d. The switch controls the operation of the device as a whole: when E = 1, the multiplexer works as usual, when E = 0, the node output is inactive, the multiplexer is locked. The functioning of the multiplexer is described by the expression:

Rice. 6. 24. Structural diagram of the multiplexer

On fig. 6.25 a, b shows two examples of the implementation of the multiplexer model. In the first case, the key consists of two lines, each of which has two “NOT” elements in series. In the second one, the DCD_2TO4 decoder is used.

Rice. 6.25 a. Multiplexer model

Rice. 6.25 b. Multiplexer model


Triggers are devices that have two stable states ( Q = 1 and Q = 0) and are able to stay in one of them for an arbitrarily long time and move from one state to another under the influence of external signals. Which of these states the trigger will be in depends on the signals at the inputs of the trigger and on its previous state, i.e. he has a memory. Thus, the trigger is an elementary memory cell.

The trigger type is determined by the algorithm of its operation, depending on which the trigger can have setting, information and control inputs. The set inputs determine the state of the trigger, regardless of the state of the other inputs. The control inputs allow the recording of data fed to the information inputs. The most common triggers are RS -, JK- , D – and T -types.

An RS flip-flop is the simplest automaton with memory that can be in two states. The trigger has two setting inputs: setting S ( set – installation) and reset R ( reset – reset), which receive input signals from external sources. When an active logic level is applied to the settings, the trigger is set to one ( Q = 1, Q ′ = 0, here the prime means inversion), when an active level is applied to the reset input, the trigger is set to zero ( Q = 0, Q ′ = 1). If a passive logic level is applied to both installation inputs, then the trigger saves the previous state of the outputs: Q = 1 or Q = 0. Each state is stable and supported by feedback. Applying an active level simultaneously to both installation inputs is prohibited, since the trigger cannot be set to zero and one.

RS -trigger can be performed on the elements “OR-NOT” or “AND-NOT” (Fig. 6.26).

a b

Rice. 6.26. RS -trigger: a – on the elements “OR-NOT”, b – on the elements “AND-NOT”

Rice. 6.26. Simulating an RS flip-flop in Multisim

For RS -flip-flops made on the elements “OR-NOT”, the active level on the control inputs is the level of logical unit, and on the elements “AND-NOT” – the level of logical zero.

RS -trigger – the main node for building sequential circuits. Conditions for transitions of triggers from one state to another can be described in tabular, analytical or graphical ways. Table 6.1 and 6.2, respectively, where Q t is the previous output state; Q t +1 is a new state that is established after the transition; – is an indeterminate state.

T a b l e 6.1 T a b l e 6.2

R S Qt+1 R S Qt+1

The JK-type flip-flop has a more complex structure and more opportunities compared to the RS -type flip-flop. In addition to information inputs J and K and direct and inverse outputs Q and Q ′, the JK flip-flop has a control input C (clocking or counting) and two asynchronous setting inputs R and S . Usually the active levels of the set signals are zeros. The setting inputs have priority over the other inputs. The active level of the signal at the input S sets the trigger to the state one ( Q = 1), and at the input R to the state zero ( Q = 0), regardless of the signals at the other inputs. If a passive signal level is applied to the inputs of the setup, then the state of the trigger will change along the edge of the pulse at the counting input, depending on the state of the inputs J and K.

One of the options for the functional diagram of the JK flip-flop and its conditional graphical representation are shown in Fig. 6.27, timing diagrams of its operation at R = S = 1 – in fig. 6.28.

Rice. 6.27. JK -trigger: a – functional diagram; b – conditional
graphic designation

Rice. 6.28. Timing diagram of the JK flip-flop

Rice. 6.29. Modeling a JK flip-flop in Multisim

The D-flip-flop has one information input D ( data – data) and one counting input C . Information from input D is written to the trigger on the positive edge of the pulse at the counting input and is stored until the next positive edge. In addition to counting C and information D inputs, the flip-flop has two asynchronous setting inputs R and S. Installation inputs have priority. The active level of the signal at the input S sets the trigger to the state of one ( Q =1), and at the input of R to the state of zero (Q=0), regardless of the signals at the other inputs.

The symbol for a D -flip-flop with diagrams of input and output signals is shown in fig. 6.30.

Rice. 6.30. D -trigger: a – symbol; b – timing diagrams

Rice. 6.31. Modeling a D-flip-flop in Multisim

T-trigger , or counting trigger , is a device that implements a counting mode. Such circuits can be built on the basis of JK – or D -flip-flops.

In a D -trigger, the counting mode (Fig. 6.32, but ) is implemented using feedback, when a signal is applied to the input D from the inverse output of the trigger, i.e. there is always an inequality of signals at the input D and at the output Q (if Q =1, D =0 and vice versa). Therefore, with each positive signal transition at the counting input C , the output state will change to the opposite.

Rice. 6.32. T -trigger: a – symbol; b – timing diagram

Thus, for every two input clock pulses, the T -flip-flop generates one period of the output signal Q , i.e. the period of the output signal is twice the period of the input signal. Therefore, the trigger divides the frequency f t at its input into two: f Q = f t /2, where f Q is the pulse repetition rate at the output of the trigger.

Rice. 6.33. Modeling a T-flip-flop in Multisim


A trigger register is a set of triggers with certain connections between them, in which they act as a single device. Registers are executed on synchronous flip-flops JK – or D -type. Depending on the functions performed, the registers are divided into storage (parallel) and shift.

In a sequential register, the output of the previous trigger is fed to the input of the next trigger, and the clock pulses are fed to the inputs C of all triggers that make up the register simultaneously (Fig. 6.34). In this case, the content of each trigger is written to the subsequent trigger. Such registers are called shift registers, or shift registers.

Rice. 6.34. Serial register (shift register)

Rice. 6.35. Modeling a Serial Register in Multisim

If a unit is applied to the input D of the shift register, and a clock frequency is applied to the input C , then the unit will begin to move along the shift register, i.e. under the influence of the first clock pulse, the unit will be written to the first trigger of the register. Under the influence of the second clock pulse, this unit will be rewritten to the second flip-flop, etc., when, under the influence of the N -th clock pulse, the unit does not leave the shift register. The timing diagram of the four-bit shift register is shown in fig. 6.36.

Rice. 6.36. Timing diagram of a four-bit shift register

Types of shift registers:

with serial input and output;

with serial input and parallel output;

with parallel input and serial output;

· with variable shift direction (reversing shift registers).

In addition to serial shift registers, there are parallel shift registers, in
which information is fed simultaneously to all N triggers and is read simultaneously from the outputs of all triggers of the register (Fig. 6.37). The clock frequency is applied simultaneously to all flip-flops.

Rice. 6.38. Simulating a Parallel Register in Multisim

Parallel registers are used to store small amounts of binary information for a short period of time.


A counter is a device that counts the number of input pulses. The number represented by the state of its outputs on the edge of each input pulse changes by one. The counter consists of n sequentially connected counting flip-flops, and the output of one counting flip-flop is connected to the clock input of the next flip-flop. Counters are summing (direct counting) and subtracting (reverse counting). In summing counters, each input pulse increases the number at its outputs by one; in subtractive counters, it decreases this number by one. In order to build a summing counter, it is necessary to connect the counting input of the next trigger to the inverse output of the previous one (Fig. 6.39).

Rice. 6.39. Summing counter and diagram of its operation

Rice. 6.40. Simulating a Totalizer in Multisim

In order to change the counting direction (implement a subtractive counter), it is necessary to connect the counting input of the next trigger to the direct output of the previous one, while changing the trigger switching sequence (Fig. 6.41).

The counter is characterized by the number of states during one period (cycle). For binary counters, the full cycle of counting N =2 n from the state 0..000 to the state 1…11. The number of states is called the conversion factor K sch , equal to the ratio of the number of pulses N s at the input to the number of pulses N Q st at the output of the most significant digit for the period:


Rice. 6.41. Subtractive counter and diagram of its operation

Rice. 6.42. Simulating a Subtractive Counter in Multisim

The counter is characterized by the number of states during one period (cycle). For binary counters, the full cycle of counting N =2 n from the state 0..000 to the state 1…11. The number of states is called the conversion factor K sch , equal to the ratio of the number of pulses N s at the input to the number of pulses N Q st at the output of the most significant digit for the period:


If a periodic sequence of pulses with a frequency f s is fed to the counter input, then the frequency f Q at the output of the counter’s most significant digit will be less than K sch times: K sch = f s / f Q . Therefore, the counters are also called frequency dividers, and K mid is the division factor. To increase the value of K sch , you need to increase the number of triggers in the chain. Each additional trigger doubles the number of states of the counter and the number K sch .


A combinational circuit is a logical circuit that implements a one-to-one correspondence between the values of input and output signals. The decoder is a logical combinational circuit with n information inputs and 2 n outputs. Each combination of logic levels at the inputs will correspond to an active level at one of the 2 n outputs. Like any logic circuit, a decoder can be defined by a truth table. The truth table of the 3×8 decoder (Table 6.3) consists of three columns corresponding to the input signals X 0 , X 1 , X 2 , and eight columns corresponding to the output signals Y 0 , Y 1 , Y 2 , Y 3 , Y 4 , Y 5 , Y 6 , Y 7 . The first three columns on the left contain possible combinations of input signals, and the last eight columns contain the corresponding combinations of output signals.

T a b l e 6.3

The circuit has eight outputs, on one of which the potential is high, on the rest it is low. The number of the only high potential output corresponds to the binary number generated by the states of the input signals. This principle of generating the output signal can be described as follows: Y i = 0 if i = k ; Y i = 1, if ik , here i is the digit number; k = 2 2 X 2 + 2 1 X 1 + 2 0 X 0 .

Expressions for each decoder output:

where “¯” is the inversion.

Thus, the decoder circuit must contain three “NOT” circuits and eight “3I” circuits (Fig. 6.43).

Rice. 6.43. 3×8 decoder circuit

Rice. 6.44. Modeling a 3×8 decoder in Multisim

Digital analyzer

Digital (logical) analyzer – a device designed to diagnose digital circuits. LA allows you to monitor and record the states of logical elements of digital electronic devices, analyze and visualize them. The appearance and front panel of the aircraft are shown in fig. 6.45.

Rice. 6.45. Logic analyzer

The aircraft has 16 channels for picking up signals, as well as several trigger inputs. In addition, the device is equipped with two cursors that allow measurements in the time domain. If input 1 is considered the least significant bit, and input 16 is the most significant, then the state of all inputs can be represented by a 16-bit binary code. The code corresponding to the cursor position is displayed in the “input code” field (Fig. 6.46).

When you press the “Set” button in the Clock group (clock generator), a dialog box opens for setting the parameters for clocking input signals (Fig. 6.47).

Signals are clocked using an external (External) or internal (Internal) source. The Clocl Qualifier field sets the active level of the clock signal. The Clock Rate field sets the analyzer’s sampling rate.

Rice. 6.46. Logic analyzer control panel

The Sampling Setting group defines signal sampling parameters:

· Pre-trigger Samples – data is collected before the trigger pulse arrives;

· Post-trigger Samples – data collection starts after the trigger pulse arrives and continues until the specified number of samples is collected;

· Treshold Volt (V) – threshold value;

Rice. 6.47. Setting sync options

Additional conditions for launching the analyzer are carried out using the Trigger Settings dialog box (Fig. 6.48). This window is used to configure the mask used to filter logic levels and synchronize input channels.

Rice. 6.48. Setting advanced sync options

Be First to Comment

Leave a Reply

Your email address will not be published.